The present invention relates to methods and structures for reducing the area of semiconductor devices, and more particularly to methods and structures developed to improve area efficiency of semiconductor devices using through-hole connections.
Semiconductor electrical diodes are commonly used for rectifying circuits and for electrostatic discharge (ESD) protections. By definition, an electrical diode is a two-terminal rectifying semiconductor device used for rectifying or for ESD protection. Examples of electrical diodes include P-N junction electrical diodes, Schottky diodes, and breakdown diodes such as transient-voltage-suppression (TVS) electrical diodes, avalanche diodes, or Zener diodes. Optical devices such as solar cells, optical or infrared sensors, and light emitting diodes (LED) are not considered electrical diodes because their major functions are optical instead of electrical. FIG. 1(a) shows a schematic symbol of a P-N junction electrical diode or a Schottky diode; FIG. 1(b) shows a schematic symbol for a breakdown diode. One of the methods to make a break down diode is to increase the doping density of junction diodes. Another common method is to connect the base and emitter of a bipolar junction transistor (BJ) as shown in FIG. 1(f). Sometimes a resistor (Rbe) is placed between the base and emitter of the bipolar transistor (BJ) as shown in FIG. 1(f). Due to transistor snap back mechanisms, the devices in FIGS. 1(f, g) can function as equivalent circuits of breakdown diodes. The same symbol in FIG. 1(b) is used to represent TVS diodes, avalanche diodes, Zener diodes, bipolar transistors with shorted emitter/base, or other types of diodes that are designed to break down safely at pre-defined ranges of reverse biased voltages; these diodes are called “breakdown diodes” in this patent application. FIG. 1(c) shows an exemplary electrical diode circuit that is a rectifier using 4 electrical diodes.
Electrostatic discharge (ESD) is the sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field. ESD is a serious issue in solid state electronics, such as integrated circuits (IC). State of the art integrated circuits comprise high performance components with dimensions measured in nanometers (nm). Such high sensitive circuit components are not designed to survive ESD attacks. They are typically isolated from external connections to avoid ESD damage. IC input and/or output (I/O) circuits that are exposed to external environments are typically thick gate, long channel, low performance devices manufactured by processes different than those for high performance core circuits. In addition, on-chip ESD protection circuits such as snap-back transistors and electrical diodes are used to protect I/O circuits from ESD attacks. Circuits designed to survive ESD attacks and circuits designed for performance have conflicting requirements. The super-fine precision of advanced IC technology makes ESD protection more difficult. For example, the nano-meter contacts and vias used in advanced IC technologies often become the weak spots during ESD attacks. To build ESD tolerant components, additional manufacture steps (ESD implant, silicide block, thick gate transistors, . . . ) are required to support ESD tolerant circuits. Therefore, on-chip ESD protection circuits occupy significant areas, require additional manufacture steps, and cause performance problems. It is therefore highly desirable to provide ESD protection chips external to integrated circuit chips in order to replace or to simplify on-chip ESD protection circuits.
By definition, a “chip” is a packaged semiconductor device that is ready for board level assembly. Therefore, a chip comprises semiconductor devices as well as conductor leads and protection materials packaged around the semiconductor devices. A die without packaging is therefore not a chip. By definition, “external electrostatic discharge (ESD) protection circuits” are ESD protection circuits that are produced to protect circuits that are external to the chip that comprises the ESD protection circuits.
Traditional ESD protection devices include snap-back transistors and electrical diodes. Electrical diodes used for ESD protection devices are used as examples of preferred embodiments in this patent application. External ESD protection chips have been developed using electrical diodes as the major protection components. For example, Texas Instruments (TI) TPD4E001 is an external ESD protection chip that can protect 4 I/O signals. FIG. 1(d) shows a schematic diagram for TI TPD4E001. This device has 4 I/O pins (IO1-IO4), one power supply pin (VDD) and one ground pin (VSS). The first I/O pin (IO1) is connected to two electrical diodes (DD1, DS1); electrical diode DD1 is connected to power supply pin (VDD), and electrical diode DS1 is connected to the ground pin (VSS), as shown in FIG. 1(d). Similarly, the other three I/O pins (IO2-IO4) are connected to electrical diodes (DD2-DD4) that are connected to the power supply pin (VDD) and electrical diodes (DS2-DD4) that are connected to the ground pin (VSS). A breakdown diode (ZD1) is connected between VDD and VSS, as shown in FIG. 1(d). At normal operation conditions, all the electrical diodes (DD1-DD4, DS1-DS4, ZD1) are under reverse biased conditions with high impedances. If a negative charge is placed on IO1 during ESD attack, DS1 is forward biased and provides a safe path to discharge to ground. If a positive charge is placed on IO1 during ESD attack, DD1 is forward biased and ZD1 breakdown, which provides safe paths to discharge to VDD and/or ground. The protection mechanisms are similar for other I/O pins (IO2-IO4).
ESD protection electrical diodes also can be integrated with other types of circuits. For example, Texas Instruments SLLS876 comprises 6 channels of ESD protection circuits integrated with electromagnetic interference (EMI) filters in one chip. FIG. 1(e) shows a schematic diagram for one channel of the TI SLLS876 EMI/ESD protection chip. The channel input (Ch_In) of the device is connected to a breakdown diode (ZD41), a capacitor (C41) and a resistor (R41), while the channel output (Ch_Out) is connected to another breakdown diode (ZD42), another capacitor (C42), and the other terminal of R41. The other terminals of ZD41, C41, C42, ZD42 are connected to ground, as shown in FIG. 1(e). The resistor (R41) and the two capacitors (C41, C42) form an EMI filter. “Pi” filter is used in this example while “T” filter is also commonly used for this application. Sometimes, the parasitic capacitors of the diodes (ZD41, ZD42) are used to serve the functions of the capacitors (C41, C42) of the EMI filters. The breakdown diodes (ZD41, ZD42) provide ESD protections to circuits connected to Ch_In and Ch_Out. If a negative charge is placed on Ch_In during ESD attack, ZD41 is forward biased and it provides a safe path to discharge to ground. If a positive charge is placed on Ch_In during ESD attack, ZD41 provides a safe path to discharge to ground using the breakdown mechanism of the breakdown diode. If a negative charge is placed on Ch_Out during an ESD attack, ZD42 is forward biased and it provides a safe path to discharge to ground. If a positive charge is placed on Ch_Out during an ESD attack, ZD42 provides a safe path to discharge to ground using the breakdown mechanism of the breakdown diode.
These and other external ESD protection devices are typically manufactured by IC technologies that are optimized for ESD protection circuits. FIGS. 2(a-e) are simplified symbolic diagrams illustrating exemplary manufacture steps for prior art ESD protection chips. FIG. 2(a) is a simplified view of a single-crystal semiconductor substrate (209) that comprises a plurality of dice (200). A die (200) is a repeating unit on a substrate that can be sliced to support a chip. A common example of single-crystal semiconductor substrate is silicon wafer. FIG. 2(b) shows a magnified picture of the marked area of the wafer in FIG. 2(a). In this example, the die (200) in the semiconductor substrate (209) is separated by scribe lanes (208) from other dice; and bonding pads (212) on the surface of the die provide openings for external connections. After the electrical diodes and other electrical components have been manufactured on the semiconductor substrate (209), the die (200) in the wafer is sliced along the scribe lanes (208) to serve as an individual device. FIG. 2(c) is a simplified symbolic diagram for one sliced die (200). In this example, the die (200) comprises 4 channels (210) of ESD/EMI circuits with components shown by the schematic in FIG. 1(e). A channel (210) in the die (200) comprises two bonding pads (212), two breakdown diodes (201), two capacitors (202), and one resistor (203) as illustrated in FIG. 2(c). Sometimes the capacitors (202) can be replaced by parasitic capacitors without using separated capacitor devices. For clarity, in FIG. 2(c) and in other figures, simplified symbols are used to represent structures that can be very complex. The structures of semiconductor components (222) are not discussed in detail. The bonding pads (212) provide openings on the semiconductor substrate for external connections to the circuit components (222) on the semiconductor substrate. Two ground and/or power pads (216) provide ground and/or power connections.
External ESD protection circuits are typically manufactured by IC manufacture processes on single crystal semiconductor substrates. The technologies used to manufacture external ESD circuits are optimized for ESD protections. Therefore, external ESD protection chips are typically more effective against ESD attacks than typical on-chip ESD protections. On-chip ESD protection typically can pass human body model ESD tests at 2000 volts, while external ESD protection chips typically can pass the test at higher than 16000 volts. However, the ESD protection circuit on the semiconductor die (200) in FIG. 2(c) is not ready for application; it needs conductor leads to allow board level electrical connections to the electrical components on the die. Prior art ESD protection circuits are typically placed in integrated circuit packages to provide conductor leads for external connections. For example, TI SLLS876 is placed inside a “thin dual-in-line flat” (TDFN) package. FIG. 2(d) is the top view illustrating the structures when the die (200) in FIG. 2(c) is placed into an integrated circuit package (219) to form a chip, and FIG. 2(e) shows the cross-section view of the packaged chip along the marked line in FIG. 2(d). The bonding pad (212) on the die (200) provides openings for external connections to the electrical components (222) on the single crystal semiconductor device. Bonding wires (218) connect the bonding pads (212) to metal traces (215) in the package (219). Such package level metal traces (215) are typically called “lead frames”. The lead frames (215) are connected to external metal pins (214) at the edges of the package as illustrated in FIGS. 2(d, e). Ground connection (216) in this example is connected to a metal pad (216) at the bottom of the TDFN package through another bonding wire (211). Some chips may use pins to support ground connections.
Although prior art ESD protection chips have been proven to be highly effective against ESD attacks, their usage is limited. The most important reason is the area of prior art ESD chips are too large. External ESD protection chips use circuits manufactured on single crystal semiconductor substrates that are placed in IC packages. The sizes of prior art external ESD protection chips are similar to those of IC chips at equivalent I/O counts. For example, TI TPD6F002 uses a package that is 3 mm by 1.35 mm. There is typically not enough room to place such prior art external ESD chips to protect a large number of signals. For these reasons, prior art external ESD protection chips are only used for a small number of special signals, such as RF signals, or for special applications. ESD circuits are integrated into chips in order to save circuit board area for applications such as cellular phones. The capabilities of mobile devices typically are determined by the capability to pack chips into a small space. Therefore, the capability to reduce the area of external ESD protection chips is typically the most important factor in determining the value of ESD protection chips or diode chips. The electrical industry has invested tremendous efforts trying to reduce the area of ESD chips using various IC packaging technologies. The present invention discloses effective methods and structures to reduce areas of ESD protection chips or electrical diode chips by printing technologies.
Prior art external ESD protection chips use single crystal diode circuits that are placed in IC packages. The costs of prior art external ESD protection chips are therefore similar to those of IC chips at equivalent I/O counts. It is typically more cost effective to use on-chip ESD protections than to use prior art external ESD protection chips. The bonding wires and the lead frames in the integrated circuit packages typically introduce parasitic inductance around 2 nh and parasitic capacitance around 2 pf—values that are large enough to cause problems for high performance signals. It is therefore highly desirable to reduce the costs and the parasitic impedances of external ESD protection chips.
One prior art method to reduce the size and the parasitic impedance of external ESD protection chips is to use ball grid array (BGA) packages. For example, TI places two breakdown diodes into one BGA package that is 1.2 mm by 1.2 mm in area. FIG. 2(f) shows exemplary cross section structures when the die (200) in FIG. 2(c) is placed in a BGA package (240). In this example, the semiconductor die (200) is placed upside down on top of a BGA substrate (242). To reduce parasitic impedance, bumping balls (245), instead of bonding wires, are used to form connections between bonding pads (212) on the die (200) and metal traces (246) on the BGA substrate (242). The metal traces (246) are connected to soldering balls (249) through vias (247) and pads (248) on the BGA substrate (242). BGA packages are typically smaller than TDFN packages, but the cost of BGA packages are typically higher than TDFN packages of the same I/O count. Sometimes bonding wires are used to form connections between the bonding pads (212) and the metal traces (246) at a lower cost but higher parasitic impedances.
The above examples show that formation of conductor leads is the major source of area, cost, and performance problems for prior art external ESD protection chips or electrical diode chips. “Conductor leads” of a chip, defined in this patent application, are the electrical conductors in a packaged chip that provide electrical connections from internal circuits to board level circuitry external to the chip. For the prior art example in FIGS. 2(d, e), a “conductor lead” comprises bonding wire (218), lead frame (215), and package pin (214). For the prior art example in FIG. 2(f), a “conductor lead” comprises a bumping ball (245), metal trace (246), via (247), pad (248), and soldering ball (249). Such complex conductor leads on integrated circuit packages typically result in large size, high cost, and high parasitic impedance. It is therefore desirable to use other methods to provide packaging for ESD protection chips or electrical diode chips.
Technologies similar to the printing technologies used for publication have been developed to manufacture passive electrical circuit components such as resistors, capacitors, or resistor-capacitor (RC) filters. FIGS. 8(a-e) are simplified diagrams illustrating examples of various electrical printing technologies. FIG. 8(a) shows a printing method where a roller (893) with a print pattern (894) rolls over a substrate (891). The substrate can be ceramic, metal, plastic, paper, semiconductor, or many other types of materials. Inks selectively attached on the roller (893) are printed on the substrate with the desired pattern (895) as illustrated on FIG. 8(b). Blocks, plates, films, or other types of printing media can also be used for printing in place of rollers. Besides rolling, printing media can have various motions. For example, print by “stamping” typically means print by linear motions of blocks, plates, or films. Electrical printing technologies are similar in principle to publication printing technologies except that the ink used by electrical printing comprises electrical materials so that dried-ink would function as conductors, insulators, resistors, dielectrics, or semiconductors. Electrical devices can be manufactured at low cost by printing layer(s) of electrical materials with desired patterns.
There are other variations of electrical printing technologies, such as screen printing and inkjet printing. Screen printing is a printing technique that uses a woven mesh to support an ink-blocking stencil. The attached stencil forms open areas of mesh that transfer ink as an image onto a substrate. When screen printing is used to manufacture electrical circuit components, materials with different electrical properties, such as conductors, insulators, resistors, or semiconductors, are mixed with solutions as ink and patterned onto a substrate by screen printing. FIGS. 8(c, d) are simplified symbolic illustrations of screen printing technologies. A stencil (802) with the desired printing pattern (804) is placed on top of a substrate (801) as illustrated in FIG. 8(c). Typical materials for stencils include woven meshes of silk or steel. The substrate can be ceramic, metal, plastic, paper, semiconductor, or many other types of materials. A roller (803) or other mechanism presses ink through the printing pattern (804). After the stencil (802) is removed, a patterned desired material (805) is printed on the substrate (801) as illustrated in FIG. 8(d). Typically, heating and drying processes are applied to solidify the printed materials. The final materials patterned by screen printing or other types of printing processes are typically “dried-ink” that was in liquid or paste form when printed and became solid form after heat treatment or other types of drying processes. Multiple layers of dried-ink materials can be printed on the same substrate using similar processes to form electrical components.
FIG. 8(e) is a simplified diagram illustrating an inkjet printing method. In this example, a printer head (812) injects electrical materials as ink (813) onto a substrate (811) to form a desired pattern (815). The locations and shapes of the printed patterns are controlled using a mechanism similar to those in computer inkjet printers.
FIGS. 8(f-h) illustrate a printing method called “dipping”. Most printing technologies involve application of ink on flat substrates. Dipping is a variation of printing technology that dip printing objects into ink. FIG. 8(f) illustrates the situation when ink lines (831) in liquid or paste form are printed on a flat surface, and a substrate (830) is moved toward the ink lines (831). The substrate (830) is stopped when it is dipped into the ink lines (831), as illustrated in FIG. 8(g). When the substrate (830) is removed from the ink lines (831), ink with the desired pattern (833) stick to the edges of the substrate (830) as illustrated in FIG. 8(h). After heat treatments, dried-ink materials in solid form are deposited and patterned on the edges of the substrate (830). The shape of printed structure depends on the ink pattern as well as the shape of the substrate. Sometimes the ink is spread across the whole surface without shape. Sometimes the ink pattern can be very complex. FIGS. 8(f-h) are symbolic diagrams illustrating simplified views of dipping of a single substrate. In practice, a large number of substrates are dipped into ink of different patterns. Dipping is a printing technology that is typically used to build conductor leads at the side-wall of chips. The present invention also applies dipping for insulators. Besides dipping into inks, it is also applicable to dip into other types of materials such as photo-resist materials.
For clarity, simplified symbolic figures are used to describe complex technology, while details such as material processing, temperature control and precision control are not included in our discussions. Printing, by definition, comprises three basic steps: (1) preparing ink that comprises desired electrical material(s) mixed with liquid solution(s) or paste(s); (2) patterning the ink in liquid or paste forms on the surface of desired object; and (3) drying the ink to remove solution in the ink to form desired dried-ink materials as solid electrical materials. Examples of electrical printing technologies include screen printing, inject printing, stamping, flexography, gravure, dipping, or offset printing.
Resistor chips in surface mount packages have been manufactured by printing technologies. FIGS. 3(a-f) are simplified illustrations for the manufacturing of surface mount resistor chips using printing technologies. The first step is typically to print patterned conductors (301) on a substrate (300) as illustrated in FIG. 3(a). Alumina is a common substrate material. Silver pastes are common materials used as the ink for conductors. Heat treatments at a temperature and timing profile specified by manufacturers are typically applied after each printing process to transform the conductor inks into dried-ink electrical conductors. The next step is to print resistor films (302) between the conductors (301) as illustrated in FIG. 3(b). Silver and Palladium alloy is an example of the material used for printed resistors. The geometry and the sheet resistance of the resistor films (302) determine the resistance values. After heat treatments, a protective insulator layer (303) is typically printed to cover the resistor layer (302) as illustrated in FIG. 3(c). Epoxy resin is a typical material used for the protective insulator layer. The next step is to print an electrode layer (304) to cover the exposed conductor plates (301) as illustrated in FIG. 3(d). Nickel is a common material for the electrode layer (304). After electrical components have been printed, the substrate (300) is sliced into individual chips (310) as illustrated in FIG. 3(e). In this example, the chip (310) in FIG. 3(e) comprises the circuits in the area marked by dark lines on the substrate (300) in FIG. 3(d). Sometimes, a side-wall conductor (305) is printed by stamping or deposited by dipping after slicing. FIG. 3(f) shows simplified cross section structures along the line marked in FIG. 3(e). FIG. 3(g) shows three dimensional external views for printed chips such as the resistor chip in FIG. 3(e). For this example, each resistor chip (310) comprises 8 edge conductor leads (365) to support 4 resistors. An “edge conductor lead”, by definition, is a conductor lead deposited on and connected to the edge(s) of the surface(s) of a surface mount package chip. The conductor leads illustrated in FIGS. 3(q-k) and FIGS. 4(g, h) are examples of edge conductor leads. The conductor leads shown in FIG. 2(f) or FIG. 5(c) are not “edge conductor leads” because they are placed in the middle of the chip without extending to the edge(s) of the chip. Using edge conductor leads typically leads to smaller chip sizes and excellent mechanical properties after soldering on printed circuit boards (PCB). The edge conductor leads (365) that provide board level I/O connections to the resistor chip (310) comprise conductors (304, 305, 301) that directly contact electrical components in the chip; no bonding wires, lead frames, or pins are used. The parasitic inductance of such connections is typically much lower than the parasitic inductance of the package connections on integrated circuit packages. A resistor chip typically has 1 to 8 resistors. FIG. 3(h) shows an exemplary three dimensional view of a two-I/O printed chip such as a resistor chip with one resistor. The size of an 8-I/O chip is roughly 4 times the size of a 2-I/O chip. There are various designs of printed circuit chips. Sometimes, side-wall conductors (375) are printed by stamping or deposited by dipping to extend the edge conductor leads, as illustrated by the chips (370, 378) in FIGS. 3(l, j). Sometimes, grooves (385) are added between edge conductor leads, as illustrated by the chip (380) in FIG. 3(k). Sometimes, the side-wall conductors are deposited in the grooves instead of between grooves. Chips with similar structures are also used for other electrical components such as resistor-capacitor (RC) filters.
The electrical industry is using a widely accepted naming convention that is related to the dimensions of resistor chips or other printed circuit chips. This naming convention uses two digit numbers related to the length (RL1, RL) of the chip followed by two or three digits related to the width or I/O pitch (RW1, RW) of the chip. For example, if the chip (368) in FIG. 3(h) is a standard “0402” resistor chip, then the length of the chip (RL1) should be about 0.04 inches, while the width of the chip (RW1) should be about 0.02 inches. The thickness (RH1) of the chip is relatively less important so it is typically not specified in the naming convention. For chips with more than two I/O edge conductor leads, the naming of the chips are typically related to the length (RL) between the ends of the opposite pair of edge conductor leads and the pitch between nearby edge conductor leads (RW), as illustrated in FIG. 3(g). For example, if the chip (310) in FIG. 3(g) is a standard 0402 resistor chip, then the length (RL) between the ends of the opposite pair of edge conductor leads should be about 0.04 inches, while the pitch between nearby edge conductor leads (RW) should be about 0.02 inches. The thickness (RH) of the chip is relatively less important so it is not specified in the naming convention. Table 1 lists commonly available resistor chips and their dimensions. For example, if the chip (368) in FIG. 3(h) is a standard “0402” resistor chip, then the length of the chip (RL1) should be about 0.04 inches, while the width of the chip (RW1) should be about 0.02 inches. If the chip (310) in FIG. 3(g) is a standard 0402 resistor chip, then the length (RL) between the ends of opposite pair of edge conductor leads should be about 0.04 inches, while the pitch between nearby edge conductor leads (RW) should be about 0.02 inches. For another example, if the chip (368) in FIG. 3(h) is a standard “0201” resistor chip, then the length of the chip (RL1) should be about 0.024 inches, while the width of the chip (RW1) should be about 0.012 inches. If the chip (310) in FIG. 3(g) is a standard 0201 resistor chip, then the length (RL) between the ends of opposite pair of edge conductor leads should be about 0.024 inches, while the pitch between nearby edge conductor leads (RW) should be about 0.016 inches. For another example, if the chip (368) in FIG. 3(h) is a standard “01005” chip, then the length of the chip (RL1) should be about 0.016 inches, while the width of the chip (RW1) should be about 0.008 inches. This industry naming standard has been widely used to describe the dimensions of not only resistor chips but also other types of printed electrical circuits such as RC components. This patent application will follow this industry standard to describe dimensions of ESD chips or electrical diode chips with printed edge conductor leads.
TABLE 1standard dimensions of surface mount resistor chipsDistance between opposite edgewidth inPitch innameconductor leads in inchesinchesinches06030.0630.0310.03104020.040.020.0202010.0240.0120.016010050.0160.0080.012
In the electrical industry, packages shown in the above examples are commonly called “surface mount rectangular passive component” (SMRPC) packages because they are typically used for surface mount passive components such as resistor chips, capacitor chips, or resistor-capacitor (RC) chips. SMRPC packages are typically significantly smaller and cheaper than integrated circuit packages or electrical diode packages of equivalent I/O count. The major reason is that the conductor leads for SMRPC packages are typically edge conductor leads. Printing technologies, such as screen printing, inject printing, stamping, flexography, gravure, dipping, or offset printing, have been applied to print passive electrical components at low costs. The costs of printed circuits are typically significantly lower than the costs of circuits using integrated circuit packages. The areas of printed chips are typically smaller than the areas of packaged IC chips. Printing technologies not only can achieve smaller size and lower cost but also can reduce parasitic inductance. Edge conduct leads of printed circuit chips are typically directly printed on the substrates; there is no need to use lead frames and bonding wires. Therefore, the parasitic inductances of printed edge conductor leads are typically significantly lower than those of integrated circuit packages.
In the art of electrical designs, electrical printing technologies are often called “thick film technologies”, in contrast to “thin film technologies” commonly used for integrated circuits. That is because the thicknesses of printed films are typically thicker than 10 micrometers while the thicknesses of “thin films” commonly used in integrated circuits are typically thinner than 2 micrometers. The resolutions of electrical printing technologies are typically measured in tens of micrometers. Such resolution is certainly not enough to support the manufacture of advanced integrated circuits, but it is enough to pattern conductor leads of external ESD protection chips or rectifying diodes.
This patent application is a continuation-in-part application of previous patent applications that focused on printed conductor leads, side-wall conductor leads, and side-wall insulators for chip-scale packages. While developing manufacture processes for side-wall insulators, it was realized that derivatives of the inventions can be used to build through-hole connections. The scope of this patent application is therefore extended.
A photo-resist, by definition, is a radiation-sensitive material used in lithography processes to form patterned structures on a substrate. Photo-resist materials may be patterned by different types of radiations such as visible light, ultra-violet light, X-ray, electron beam, or ion beam. Photo-resist materials are classified into two groups: positive resists and negative resists. A positive resist is a type of photo-resist in which the portion of the photo-resist that is exposed to radiation becomes soluble to the photo-resist developer. The portion of the positive photo-resist that is unexposed remains insoluble to the photo-resist developer. A negative resist is a type of photo-resist in which the portion of the photo-resist that is exposed to radiation becomes insoluble to the photo-resist developer. The unexposed portion of the negative photo-resist can be dissolved by the photo-resist developer. The terminology “Developed photo-resist materials” used in this patent application, by definition, are the photo-resist materials that are insoluble to the photo-resist developer and remain on the substrate after the developing procedures. For a positive photo-resist, the “developed photo-resist materials” are the photo-resist materials unexposed to radiation. For a negative photo-resist, the “developed photo-resist materials” are the photo-resist materials exposed to radiation.
In this patent application, a through-hole, by definition, is an opening in a semiconductor substrate that extends from the front surface of the semiconductor substrate all the way to the back surface of the semiconductor substrate. The opening of a through-hole maybe filled with other materials after it is opened. The front surface or the front side of a substrate is the surface built with electrical devices such as integrated circuits, transistors, resistors, and/or capacitors; the back surface or the back side of a substrate is opposite to the front surface. If electrical devices are manufactured on both sides of the semiconductor substrate, then the surface with more complex electrical devices is considered as the front surface.
FIGS. 14(a-l) are simplified illustrations of conventional manufacture procedures for through-hole connections. FIG. 14(a) shows the cross-section view of a silicon substrate. For clarity, electrical components build on the substrate are not draw in our figures. FIG. 14(b) shows the cross-section view and FIG. 14(c) shows the top view when through-holes (121) are opened in the substrate (120). FIG. 14(d) shows symbolic cross-section view when insulator materials (122) are applied on the substrate (120) to fill the through-holes (121) and cover both surfaces. FIGS. 14(e-j) illustrate conventional methods for opening through-holes (127) in the insulator materials (122) using lithograph technology. Photo-resist materials (123) are deposited on the surface, as shown in FIG. 14(e), and selectively exposed to radiation (125) with patterns defined by a photo mask (124), as illustrated in FIG. 14(f). For the example in FIG. 14(f), the photo-resist is a positive photo-resist so that the areas (126) exposed to radiation become soluble to the photo-resist developer. Those exposed photo-resist materials (126) are removed after the developing procedures, as illustrated in FIG. 14(g). The remaining photo-resist materials (123) are used as etching mask so that through-holes (127) in the insulator materials (122) can be etched with accuracy, as illustrated in FIG. 14(h). The developed photo-resist materials (123) are washed away after the through-holes (127) has been opened, as illustrated in the cross section view in FIG. 14(i) and the top view in FIG. 14(j). Using similar methods, conductor films (128) can be deposited to form through-hole conductor leads, as illustrated by the cross-section view in FIG. 14(k) and the top view in FIG. 14(l).
Using conventional methods, making electrical connections using through-holes is difficult. Existing methods typically require large distances between through holes, limiting the number of through-holes per die. Conventional through-hole connections typically have poor controls in the parasitic impedances, limiting their applications for high speed applications. Trezza in U.S. Pat. No. 7,157,372 disclosed a method that fills a semiconductor through-hole with insulator, then etch a through-hole in the insulator as a method to control the impedance and to reduce the size of through-hole connections. One of the preferred embodiments of the present invention uses developed photo-resist materials to form the side walls of the through-holes. The preferred embodiments of the present invention require less manufacture steps and provide better controls in parasitic impedances than Trezza. Hanaoka et al. in U.S. Pat. No. 6,667,551 disclose a through-hole that has small opening at the front surface, and larger opening inside the semiconductor substrate. Both the smaller and the larger opening in Hanaoka were opened from the front surface. One of the preferred embodiments of the present invention opens a small hole from the front surface then opens a larger hole from the back surface to form a through hole by combining those two holes. The preferred embodiments of the present invention requires less processing steps and provides better control than Hanaoka et al.